1. Field of the Invention
The present invention relates generally to semiconductor memory devices and a manufacturing method therefor, and more particularly, to a semiconductor memory device having memory cells formed in trenches such as a dynamic random access memory and a manufacturing method therefor.
2. Description of the Background Art
In recent years, with a remarkable spread of information apparatuses such as computers, there is an increasing demand for semiconductor memory devices. In addition,.strongly demanded is a semiconductor memory device having a large memory capacity and capable of operating at a high speed. Under these circumstances, the semiconductor memory device technique improves to achieve higher integration and higher speed response or higher reliability.
Semiconductor memory devices include a DRAM (Dynamic Random Access Memory) capable of inputting and outputting storage information at random. Generally, a DRAM comprises a memory cell array which is a storage region for storing a lot of pieces of storage information, and peripheral circuits required for inputting and outputting information to and from the outside.
FIG. 52 is a block diagram showing a structure of a common DRAM. Referring to FIG. 52 , a DRAM 50 comprises a memory cell array 51, a row and column address buffer 52, a row decoder 53 and a column decoder 54, a sense refresh amplifier 55, a data-in buffer 56 and a data-out buffer 57 and a clock generator 58. The memory cell array 51 stores a data signal of storage information. The row and column address buffer 52 externally receives address signals A0-A9 for selecting memory cells forming a unit storage circuit. The row decoder 53 and the column decoder 54 designate memory cells by decoding the address signals. The sense refresh amplifier 55 amplifies and reads the signals stored in the designated memory cells. The data-in buffer 56 and the data-out buffer 57 input and output the data. The clock generator 58 generates clock signals which become control signals for the respective portions.
The memory cell array 51 occupying a large area of a semiconductor chip has a plurality of memory cells arranged in matrix for storing unit storage information. FIG. 53 is a diagram showing an equivalent circuit of 4-bit memory cells forming the memory cell array 51. The memory cell array 51 comprises a plurality of word lines WLs extending in parallel in a row direction and a plurality of bit line pairs of BL and BL extending in parallel in a column direction. Memory cells M are formed near intersecting portions between the word line WL and the bit line BL, and WL and BL. The shown memory cell M comprises one MOS (Metal Oxide Semiconductor), transistor Tr and one capacitor C. Namely, each memory cell is a one-transistor one-capacitor type memory cell. Since the memory cell of this type has a simple structure, it is easy to increase the degree of integration of a memory cell array, and therefore it is widely used in large capacity DRAMs. Such structure as shown in FIG. 53 is referred to as a folded bit line arrangement in which a bit line pair of BL and BL is disposed in parallel with a sense amplifier.
Referring to FIG. 52, data is stored in N (=n.times.m) bit memory cell array 51. Address information of a memory cell to be read/written is stored in the row and column address buffer 52, and through a selection of a specific word line (selection of one word line among n word lines]by the row decoder 53, m-bit memory cells are connected to the sense refresh amplifiers 55 through the bit lines. Then, by selecting a specific bit line (selecting one bit line among m bit lines) by the column decoder 54, one sense refresh amplifier is connected to the input/output circuit, so that reading or writing is carried out based on the instructions of the control circuit.
Referring to FIG. 53, the MOS transistor Tr has a gate electrode connected to the word line WL, one source/drain electrode connected to one electrode of the capacitor C and the other source/drain electrode connected to the bit line BL. In data writing, application of a predetermined voltage to the word line WL renders the MOS transistor Tr conductive, so that the electric charges applied to the bit line BL are stored in the capacitor C. On the other hand, in data reading, application of a predetermined voltage to the word line WL renders the MOS transistor Tr conductive, so that the electric charges stored in the capacitor C are taken out through the bit line BL.
In recent years, a remarkable progress has been made in a semiconductor memory device and with high integration and high density thereof, miniaturization of a pattern for each semiconductor element formed therein has been accelerated. There is a strong demand for a compact and large capacity semiconductor memory device operating at a high speed. In order to meet these requirements, miniaturization of a pattern of each semiconductor element becomes indispensably necessary. In particular, a memory cell of such a DRAM as described above is a representative thereof. It is necessary to reduce a semiconductor substrate area occupied by a memory cell not only by minimizing the size of each element of a transistor, a capacitor and the like, but also by minimizing the size of a memory cell formed by these elements. In order to reduce an area occupied by the memory cell region, developments have been made in various memory cell arrangements.
For the furtherance of high integration and high density, proposed is a one-transistor one-capacitor dynamic memory cell having an elongated transistor formed on a sidewall portion of a trench for capacitor, which memory cell is disclosed in "A Trench Transistor Cross-Point DRAM Cell" in IEDM Technical Digest pp. 714-717, Dec. 1-4, 1985. According to this article, since all the memory cells are buried in trenches in this DRAM, the DRAM has the most suitable structure for reducing a memory cell area in a semiconductor substrate. FIG. 54(A) is a plan view showing such DRAM and FIG. 54(B) is a partially sectional view showing a sectional structure taken by B--B of FIG. 54(A). Referring to FIG. 54(A) an n.sup.+ impurity region 103 serving as a plurality of bit lines and a gate electrode 106 serving as a plurality of word lines are arranged orthogonally intersecting with each other. A trench 101 is formed at an intersecting portion of the bit line and the word line. Each memory cell M is formed in the trench 101. Referring to FIG. 54(B), formed is a memory cell M with each element isolated by an isolation oxide film 110 on a major surface of a p type silicon substrate 102. The memory cell M comprises an n channel MOS transistor and a capacitor. The n channel MOS transistor includes n.sup.+ impurity regions 103 and 104 forming drain/source regions, a channel region 105 provided therebetween, and a gate electrode 106 formed on the channel region 105 with a gate oxide film 105a provided therebetween. The channel region 105 is provided on an outer periphery of the gate oxide film 105a and along a sidewall portion of a trench formed in the major surface of the silicon substrate 102. The capacitor comprises a capacitor electrode 120 formed so as to be connected to the n.sup.+ impurity region 104 constituting the n channel MOS transistor, a capacitor oxide film 130 and the p type silicon substrate 102. The capacitor electrode 120 is formed of a polysilicon layer buried in the trench formed in the p type silicon substrate 102. The n.sup.+ impurity region 104 is formed into a ring-shape surrounding the capacitor electrode 120. The gate electrode 106 constituting the n channel MOS transistor is formed of an n.sup.+ polysilicon layer, which serves as a word line.
As the foregoing, in the memory cell shown in FIG. 54(B), an elongated n channel MOS transistor is formed in a sidewall portion of the trench provided for a capacitor. This is directed to reducing a plane area occupied by the n channel MOS transistor in a major surface of the substrate. It is directed to maintaining performance of the transistor, for example, by forming a channel region in a sidewall portion of a trench without making the transistor itself smaller.
However, in this structure, the isolation oxide film 110 is formed on the major surface of the silicon substrate 102 in order to isolate the respective memory cells M. In addition, the word line 106 is formed on the isolation oxide film 110. Furthermore, the n.sup.+ impurity regions 103 serving also as bit lines are formed at the opposite sides of the isolation oxide film 110. Therefore, the word line 106 formed just on the isolation oxide film 110 and the n.sup.+ impurity regions 103 formed at the opposite sides of the isolation oxide film 110 form a parasitic MOS transistor. Namely, a MOS transistor using the p type silicon substrate as a substrate, the isolation oxide film 110 as a gate insulation film and the word line 106 as a gate electrode is formed between the two n.sup.+ impurity regions adjacent to each other with the isolation oxide film 110 provided therebetween. In order to isolate the elements of each memory cell completely, the parasitic MOS transistor should be completely cut off in the range of an operation voltage of a DRAM. However, as long as the parasitic MOS transistor is formed as shown in FIG. 54(B), as a width of the isolation oxide film 110 is miniaturized below submicron order, it becomes more and more difficult to electrically isolate the memory cells. Unless this problem is overcome, it is difficult to manufacture a large capacity DRAM larger than that of 64 M bits in the future.